Devadas Varma

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. AutoESL provides the fastest path from algorithms to silicon. AutoESL provides a powerful high level synthesis solution that enables: Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs. Software architects to accelerate software algorithms by implementing them in silicon. System architects to take software models into silicon without manually writing RTL. Hardware architects to explore and implement the right architecture in silicon.

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. AutoESL provides the fastest path from algorithms to silicon. AutoESL provides a powerful high level synthesis solution that enables: Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs. Software architects to accelerate software algorithms by implementing them in silicon. System architects to take software models into silicon without manually writing RTL. Hardware architects to explore and implement the right architecture in silicon.

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. AutoESL provides the fastest path from algorithms to silicon. AutoESL provides a powerful high level synthesis solution that enables: Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs. Software architects to accelerate software algorithms by implementing them in silicon. System architects to take software models into silicon without manually writing RTL. Hardware architects to explore and implement the right architecture in silicon.

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. AutoESL provides the fastest path from algorithms to silicon. AutoESL provides a powerful high level synthesis solution that enables: Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs. Software architects to accelerate software algorithms by implementing them in silicon. System architects to take software models into silicon without manually writing RTL. Hardware architects to explore and implement the right architecture in silicon.

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. AutoESL provides the fastest path from algorithms to silicon. AutoESL provides a powerful high level synthesis solution that enables: Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs. Software architects to accelerate software algorithms by implementing them in silicon. System architects to take software models into silicon without manually writing RTL. Hardware architects to explore and implement the right architecture in silicon.